Title :
A low power scheduling scheme with resources operating at multiple voltages
Author :
Manzak, Ali ; Chakrabarti, Chaitali
Author_Institution :
Lattice Semicond. Corp., San Jose, CA, USA
Abstract :
This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n/sup 2/) algorithm and 2) a high complexity O(n/sup 2/ log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.
Keywords :
computational complexity; data flow graphs; high level synthesis; iterative methods; low-power electronics; scheduling; 1.5 V; 2.4 V; 3.3 V; 5 V; HLS; Lagrange multiplier; complexity; critical path delay; data flow graph; energy consumption; iterative method; latency constraint; low power scheduling algorithm; minimum energy relation; multiple voltage operation; node slack distribution; power consumption; resource constraint; Circuits; Delay; Energy consumption; High level synthesis; Iterative algorithms; Lagrangian functions; Scheduling algorithm; Throughput; Time factors; Voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on