False path exclusion in delay analysis of RTL structures

In this paper, we present an accurate delay-estimation algorithm at the register-transfer level. We study three important sources of false paths in register-transfer-level (RTL) structures, i.e., 1) resource binding; 2) interdependent conditions; and 3) datapath-controller path mismatching. The existence and creation of such paths and their effects in delay analysis are discussed. We show that in a RTL datapath structure the accuracy of the delay estimators is affected by the existence of false paths. Specifically, the accuracy drops significantly for structures synthesized from condition-dominated behaviors. We propose a mechanism to efficiently avoid false paths in delay analysis. This is achieved by introducing the propagation delay graph (PDG), whose traversal for delay analysis is equivalent to the traversal of sensitizable paths in the datapath. Comparison with the timing verifier in commercial computer-aided design (CAD) tools, show that estimated delays are within 14% accuracy of those reported by CAD tools.