Confined lateral selective epitaxial growth of silicon for device fabrication

Author

Schubert, Peter J. ; Neudeck, Gerold W.

Author_Institution

Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

11

Issue

5

fYear

1990

fDate

5/1/1990 12:00:00 AM

Firstpage

181

Lastpage

183

Abstract

An epitaxy technique, confined lateral selective epitaxial growth (CLSEG), which produces wide, thin slabs of single-crystal silicon over insulator, using only conventional processing, is discussed. As-grown films of CLSEG 0.9 mu m thick, 8.0 mu m wide, and 500 mu m long were produced at 1000 degrees C at reduced pressure. Junction diodes fabricated in CLSEG material show ideality factors of 1.05 with reverse leakage currents comparable to those of diodes built in SEG homoepitaxial material. Metal-gate p-channel MOSFETs in CLSEG with channel dopings of 2*10/sup 16/ cm/sup -3/ exhibit average mobilities of 283 cm/sup 2//V-s and subthreshold slopes of 223 mV/decade.<>

Keywords

elemental semiconductors; insulated gate field effect transistors; semiconductor diodes; semiconductor epitaxial layers; semiconductor growth; silicon; 1000 degC; CLSEG; channel dopings; confined lateral selective epitaxial growth; device fabrication; epitaxy technique; ideality factors; junction diodes; mobilities; p-channel MOSFETs; reverse leakage currents; subthreshold slopes; Dielectric materials; Dielectrics and electrical insulation; Diodes; Epitaxial growth; Etching; Fabrication; Planarization; Semiconductor films; Silicon on insulator technology; Substrates;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.55243

Filename

55243