Title :
Performance characteristics of SOI DRAM for low-power application
Author :
Park, Jong-Woo ; Kim, Yun-Gi ; Kim, Il-Kwon ; Park, Kyu-Charn ; Lee, Kyu-Chan ; Jung, Tae-Sung
Author_Institution :
Technol. Div. & Memory Product, Samsung Electron., Kyungki, South Korea
fDate :
11/1/1999 12:00:00 AM
Abstract :
Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 μm design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (Iccl) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit technology; low-power electronics; silicon-on-insulator; 0.3 micron; 16 Mbit; LV DRAM application; SOI DRAM; Si; body bias control schemes; cell capacitors; dynamic RAM; leakage current; low-power application; low-voltage DRAM; pattern-bonded SOI technology; performance characteristics; process integration; subthreshold swing; ultra-low-voltage transistor technology; Capacitors; Circuit optimization; Current measurement; Integrated circuit measurements; Leakage current; Pattern analysis; Performance analysis; Random access memory; Silicon on insulator technology; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
