A Comparative Study of Gate Structures for 9.4-kV 4H-SiC Normally On Vertical JFETs

This paper reports the development of 9.4-kV 4H-SiC normally on lateral-channel vertical JFETs. The developed JFETs utilize a buried layer to create a lateral conduction channel, shielding the source from the effects of drain bias. The lowest measured $R_{\rm on, sp}$ was 127 $\hbox {m}\Omega \cdot\hbox {cm}^{2}$ . Measurements indicate that the channel resistivity can be further reduced by channel optimization. The fabricated JFETs exhibit pentode-like $I_{D}$ – $V_{\rm DS}$ characteristics with a high forward direct-current blocking gain of over 500. This paper provides a comparative study of gate structures in order to achieve the lowest on -state switching losses and to provide stable forward blocking characteristics for a normally on JFET.