An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

Author

Zhao, Cangsang ; Bhattacharya, Uddalak ; Denham, Martin ; Kolonsek, J. ; Lu, Yi ; Ng, Yong-Gee ; Nintunze, Novat ; Sarkez, Kamal ; Varadarajan, Hemmige D.

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1564

Lastpage

1570

Abstract

An 18-Mbit CMOS pipeline-burst cache SRAM achieves a 12.3-Gbyte/s data transfer rate with 1.54-Gbit/s/pin I/O´s. The SRAM is fabricated on a 0.18-μm CMOS technology. The 14.3×14.6-mm² SRAM chip uses a 5.59-μm², six-transistor cell. Circuit techniques used for achieving high bandwidth include fully self-timed array architecture, segmented hierarchical sensing with separated global read/write bitlines in different metal layers, a high-speed data-capture technique, a reduced-swing output buffer, and a high-sensitivity, high-bandwidth input buffer

Keywords

CMOS memory circuits; SRAM chips; cache storage; memory architecture; pipeline processing; timing; 0.18 micron; 1.54 GB/s; 12.3 GB/s; 18 Mbit; CMOS pipeline-burst cache SRAM; CMOS static RAM; high bandwidth; high-sensitivity input buffer; high-speed data-capture technique; reduced-swing output buffer; segmented hierarchical sensing; self-timed array architecture; separated global read/write bitlines; six-transistor cell; Bandwidth; CMOS technology; Circuits; Memory architecture; Microprocessors; Phase locked loops; Random access memory; SRAM chips; Vehicles; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799864

Filename

799864