A 500-MHz pipelined burst SRAM with improved SER immunity

Author

Sato, Hirotoshi ; Wada, Tomohisa ; Ohbayashi, Shigeki ; Kozaru, Kunihiko ; Okamoto, Yasuyuki ; Higashide, Yoshiko ; Shimizu, Tadayuki ; Maki, Yukio ; Morimoto, Rui ; Otoi, Hisakazu ; Koga, Tsuyoshi ; Honda, Hiroki ; Taniguchi, Makoto ; Arita, Yutaka ; Shi

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1571

Lastpage

1579

Abstract

This paper describes a 0.25-μm, 64 K×36 bit pipelined burst SRAM using a 6.156-μm² cell. It realizes over 500-MHz operation using a lower cost double metal process, Internal 16 K×144 organization by T-shaped bit line array reduces 20% of latency, 20% of active power, and 8.5% of die size. The low power also enables us to use lower cost thin quad flat type packages. Our solution to the soft error problem, a shallow triple well structure and four-transistor cell with stacked capacitor, improved soft error rate by 3.5 orders of magnitude compared with the conventional SRAM cell

Keywords

CMOS memory circuits; SRAM chips; alpha-particle effects; capacitance; high-speed integrated circuits; low-power electronics; memory architecture; pipeline processing; synchronisation; 0.25 micron; 2 ns; 2.25 Mbit; 3.3 V; 350 to 500 MHz; 360 mA; CMOS static RAM; QFP; SER immunity; T-shaped bit line array; four-transistor cell; low power operation; pipelined burst SRAM; shallow triple well structure; soft error problem; soft error rate; stacked capacitor; thin quad flat type packages; Capacitance; Capacitors; Circuits; Costs; Delay; Error analysis; Frequency; High performance computing; Packaging; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799865

Filename

799865