A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme

Author

Takase, Satoru ; Kushiyama, Natsuki

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1600

Lastpage

1606

Abstract

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach

Keywords

CMOS memory circuits; DRAM chips; memory architecture; redundancy; 0.25 micron; 1.6 GByte/s; 72 Mbit; CMOS dynamic RAM; area efficiency; data retention power reduction; direct Rambus DRAM; flexible mapping redundancy technique; memory architecture; multibank; refresh scheme; Bandwidth; Circuits; Decoding; Delay; Latches; Magnetic resonance; Memory architecture; Microelectronics; Random access memory; Signal analysis;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799868

Filename

799868