A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller

Author

Harrand, Michel ; Sanches, Jose ; Bellon, Alain ; Bulone, Joseph ; Tournier, Alain ; Deygas, Olivier ; Herluison, Jean-Claude ; Doise, David ; Berrebi, Elisabeth

Author_Institution

STMicroelectron., Crolles, France

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1627

Lastpage

1633

Abstract

A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm² in a 0.35-μm technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign

Keywords

CMOS digital integrated circuits; data compression; digital signal processing chips; motion estimation; parallel architectures; video codecs; video coding; videotelephony; 0.35 micron; CIF pictures; CMOS DSP chip; H261; H263; H263+; codesign; dedicated programmable processors; distributed dedicated multiprocessor architecture; embedded display controller; hardware/software partitioning; picture quality; single-chip video codec; video encoder/decoder; video-conferencing recommendations; videotelephony applications; Cameras; Costs; Decoding; Displays; Hardware; ISDN; Image coding; Microprocessors; Software standards; Video codecs;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799872

Filename

799872