A single-chip universal digital satellite receiver with 480-MHz IF input

This paper presents a complete single-chip universal digital satellite receiver supporting all current DBS system standards. The mixed-signal device accepts a modulated data stream at up to 90 Mbps and delivers a demodulated, error-corrected output data stream. The IC features an analog front end with 480-MHz intermediate frequency downconversion and dual 8-bit analog-to-digital converters, an all-digital BPSK/QPSK/OQPSK variable-rate receiver supporting 1-45 MBaud operation with phase/frequency recovery, variable-rate digital filters, square-root Nyquist matched filters, acquisition and tracking loops, and a DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Reed-Solomon forward error correction decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 million transistors in a die area of 22 mm² and was implemented in a single-poly 0.35-μm CMOS process with four layers of metal