Supply noise insensitive PLL design through PWL behavioral modeling and simulation

Author

Lee, Chang-Hyeon ; McClellan, Kelly ; Choma, John, Jr.

Author_Institution

Wireless Commun. Div., Conexant Syst. Inc, Newport Beach, CA, USA

Volume

48

Issue

12

fYear

2001

fDate

12/1/2001 12:00:00 AM

Firstpage

1137

Lastpage

1144

Abstract

This brief presents a design flow for a supply noise insensitive (SNI) phase-locked loop (PLL). The influence on the PLL jitter of each noise component having high/low bandpass filter characteristics is investigated in the time domain. Acquisition time, tracking range, lock range and jitter are key parameters of a PLL system, and they are evaluated with piecewise linear (PWL) behavioral modeling. Finally, the SNI-PLL circuit having worst-case -45-dB power supply noise rejection based on the behavioral simulation results is implemented

Keywords

circuit simulation; jitter; phase locked loops; piecewise linear techniques; time-domain analysis; PLL design; PWL simulation; acquisition time; bandpass filter characteristics; behavioral modeling; jitter; lock range; piecewise linear modeling; power supply noise rejection; supply noise insensitive design; time domain; tracking range; Circuit noise; Circuit simulation; Jitter; PSNR; Phase locked loops; Phase noise; Piecewise linear techniques; Semiconductor device noise; Voltage; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.988939

Filename

988939