A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

Author

Inoue, Michihiro ; Yamada, Toshio ; Kotani, Hisakazu ; Yamauchi, Hiroyuki ; Fujiwara, Atsushi ; Matsushima, Junko ; Akamatsu, Hironori ; Fukumoto, Masanori ; Kubota, Masafumi ; Nakao, Ichiro ; Aoi, Nobuo ; Fuse, Genshu ; Ogawa, Shin-Ichi ; Odanaka, Shinji

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Moriguchi, Osaka, Japan

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1104

Lastpage

1112

Abstract

A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm² in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm² to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; 0.5 micron; 16 Mbit; 35 ns; 63 fF; 65 ns; CMOS technology; DRAM; RAS access time; column address access time; double-level metallization; dual-in-line package; dynamic RAM; memory IC; open-bit-line architecture; relaxed sense-amplifier-pitch; storage capacitance; surrounding high-capacitance cell; trench-type; Bismuth; CMOS technology; Capacitance; Capacitors; DRAM chips; Fuses; Packaging; Random access memory; Semiconductor device measurement; Semiconductor device noise;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5931

Filename

5931