The impact of data-line interference noise on DRAM scaling

Author

Nakagome, Y. ; Aoki, Masaki ; Ikenaga, S. ; Horiguchi, M. ; Kimura, Shunji ; Kawamoto, Youshifumi ; Itoh, Kiyoo

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1120

Lastpage

1127

Abstract

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond

Keywords

MOS integrated circuits; cellular arrays; electron device noise; integrated memory circuits; random-access storage; 16 Mbit; DRAM scaling; MOS IC; cell array architecture; data-line interference noise; dynamic RAM; dynamic behavior; memory chip; precise noise determination; sense-amplifier operation; Analytical models; Capacitance; Circuit noise; Data analysis; Interference; Noise level; Operational amplifiers; Random access memory; Signal analysis; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5933

Filename

5933