Title :
A 45-ns 64-Mb DRAM with a merged match-line test architecture
Author :
Mori, Shigeru ; Miyamoto, Hiroshi ; Morooka, Yoshikazu ; Kikuda, Shigeru ; Suwa, Makoto ; Kinoshita, Mitsuya ; Hachisuka, Atsushi ; Arima, Hideaki ; Yamada, Michihiro ; Yoshihara, Tsutomu ; Kayano, Shimpei
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff=5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time
Keywords :
CMOS integrated circuits; DRAM chips; 0.4 micron; 3.3 V; 30 fF; 45 ns; 64 Mbit; CMOS technology; DRAM; RAS access time; cell capacitance; cell structure; data-line architecture; double-level metallization; dual-cell-plate; dynamic RAM; gate insulator; memory chip; merged match-line test architecture; oxynitride layer; CMOS technology; Capacitance; Circuit simulation; Metallization; Mirrors; Random access memory; Read-write memory; Redundancy; Switches; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
