A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

Author

Taguchi, Masao ; Tomita, Hiroyoshi ; Uchida, Toshiya ; Ohnishi, Yasuhiro ; Sato, Kimiaki ; Ema, Taiji ; Higashitani, Masaaki ; Yabu, Takashi

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1493

Lastpage

1497

Abstract

The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data

Keywords

DRAM chips; 40 ns; 64 Mbit; 64 bit; DRAM; RAS access; column gate circuit; current-sensing; data bus amplifier; direct-sensing type; double-fin storage capacitor; double-level metallization; dynamic RAMs; hierarchical data bus structure; parallel data bus architecture; shielded bit-line; three-dimensional stacked-capacitor; wide I/O data path structure; Aluminum; Capacitance; Circuit testing; Decoding; Driver circuits; Mirrors; Power amplifiers; Power supplies; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98963

Filename

98963