A 33-ns 64-Mb DRAM

Author

Oowaki, Yukihito ; Tsuchida, Kenji ; Watanabe, Yohji ; Takashima, Daisaburo ; Ohta, Masako ; Nakano, Hiroaki ; Watanabe, Shigeyoshi ; Nitayama, Akihiro ; Horiguchi, Fumio ; Ohuchi, Kazunori ; Masuoka, Fujio

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1498

Lastpage

1505

Abstract

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm² has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 μm×1.7 μm each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved

Keywords

CMOS integrated circuits; DRAM chips; 0.4 micron; 15 ns; 33 ns; CMOS; DRAM; N-substrate triple-well; PMOS centered; RAS access time; asymmetrical stacked-trench capacitor; column address access time; double-metal process; double-poly; double-polycide; dynamic RAM; high packing density; high-speed requirements; interdigitated twisted bit-line; low noise; preboosted word-line drive-line technique; Associate members; CMOS process; CMOS technology; Capacitors; Circuit noise; Delay effects; MOS devices; MOSFET circuits; Random access memory; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98964

Filename

98964