A 64-Mb DRAM with meshed power line

Author

Yamada, Toshio ; Nakata, Yoshiro ; Hasegawa, Junko ; Amano, Noriaki ; Shibayama, Akinori ; Sasago, Masaru ; Matsuo, Naoto ; Yabu, Toshiki ; Matsumoto, Susumu ; Okada, Shozo ; Inoue, Michihiro

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1506

Lastpage

1510

Abstract

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM

Keywords

CMOS integrated circuits; DRAM chips; 0.4 micron; 3.3 V; 50 ns; 64 Mbit; CMOS technology; DRAM; KrF excimer laser lithography; crosstalk noise; dynamic RAM; memory cell structure; meshed power line; noise suppression; sense-amplifier driver; shield peripheral layout scheme; tunnel-shaped stacked-capacitor cell; CMOS technology; Capacitance; Circuit noise; Crosstalk; Degradation; Delay; Integrated circuit interconnections; Laser noise; Random access memory; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98965

Filename

98965