A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture

Author

Kimura, Katsutaka ; Sakata, Takeshi ; Itoh, Kiyoo ; Kaga, Toru ; Nishida, Takashi ; Kawamoto, Yoshifumi

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1511

Lastpage

1518

Abstract

The authors describe a block-oriented random-access memory (BORAM) based on a series-connected cell concept and a quasi-folded data-line architecture. The series-connected cell concept allows a nearly half-sized DRAM cell even when using the same fabrication process as for conventional DRAMs. The low-noise quasi-folded data-line architecture allows the data-line capacitance to be one eighth the conventional value at the minimum, or the number of cells per amplifier to be 64 times the conventional number at the maximum. In addition, this architecture provides a more relaxed layout for the READ/WRITE circuits. The operation of four series-connected cells is observed successfully through a test device which includes a voltage-to-current conversion circuit, a current-mirror amplifier, and a 0.76-μm² crown-shaped stack-capacitor (STC) cell

Keywords

DRAM chips; block-oriented RAM; crown-shaped stack-capacitor; current-mirror amplifier; dynamic RAM; half-sized DRAM cell; quasi-folded data-line architecture; quasifolded data line; random-access memory; series-connected cell; voltage-to-current conversion circuit; Capacitance; Capacitors; Circuit testing; Fabrication; Helium; Low-noise amplifiers; Random access memory; Read-write memory; Transistors; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98966

Filename

98966