Title :
A 1.2-ns HEMT 64-kb SRAM
Author :
Suzuki, Masahisa ; Notomi, Seishi ; Ono, Masaaki ; Kobayashi, Naoki ; Mitani, Eizo ; Odani, Kouichiro ; Mimura, Takashi ; Abe, Masayuki
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
A 1.2-ns emitter-coupled-logic (ECL)-compatible 64-kb static RAM using 0.60-μm gate high-electron-mobility-transistor (HEMT) technology was developed. To achieve fast access time, the memory cell array was divided into sixteen 4-kb memory planes and a data-line equalization technique was adopted. The chip power consumption was suppressed to 5.9 W by using three power supply voltages (-1.0, -2.0, and -3.6 V) and a normally off (E/D) source-follower buffer for the word driver circuit. A new device fabrication technique, the HEMT double-etch-stop process, enabled the RAM to be fabricated in simple and fewer processing steps and reduced the chip dimensions to 7.4×6.5 mm
Keywords :
SRAM chips; field effect integrated circuits; high electron mobility transistors; -1 V; -2 V; -3.6 V; 0.6 micron; 1.2 ns; 5.9 W; 64 Kbit; ECL compatible type; HEMT; SRAM; access time; chip power consumption; data-line equalization; device fabrication technique; double-etch-stop process; emitter-coupled-logic; high-electron-mobility-transistor; memory cell array; source-follower buffer; static RAM; word driver circuit; BiCMOS integrated circuits; Circuit synthesis; Decoding; Energy consumption; HEMTs; Logic arrays; MODFETs; Random access memory; Read-write memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
