A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation

Author

Kobayashi, Tsuguo ; Nogami, Kazutaka ; Shirotori, Tsukasa ; Fujimoto, Yukihiro ; Biwaki, Yoshitaka ; Nohara, Haruo ; Kobayashi, Makiji ; Kobayashi, Kiyoshi ; Sawada, Kazuhiro

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1586

Lastpage

1592

Abstract

A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible expandability was achieved by cascading multiple cache memories. The device was successfully implemented with 1.0-μm double-polysilicon and double-metal CMOS technology. Low-power sense amplifiers and comparators limited power dissipation to 0.5 W at 40 MHz

Keywords

CMOS integrated circuits; buffer storage; integrated memory circuits; 0.5 W; 1 micron; 40 MHz; 64 kbyte; CMOS technology; double word-line architecture; double-metal; double-polysilicon; low power sense amplifiers; pseudo two-port operation; single-port cell; snoopy cache memory; time-multiplex snoop operation; word-line buffers; CMOS technology; Cache memory; Costs; Laboratories; Microelectronics; Organizing; Power dissipation; Semiconductor devices; System performance; System-on-a-chip;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98976

Filename

98976