A clock duty cycle stabilizer based on DLL

Based on 0.18μm CMOS process, a clock duty cycle stabilizer is designed, which is suitable for high speed analog to digital converters (ADCs). The proposed circuit is improved from the traditional one: a new-type dynamic phase detector is used with simper construction and smaller power consumption, which eliminates the dead region which exists in the traditional phase detector; a kind of special delay cell is used to prevent false locking. The postlayout simulation shows that, working at 500MHz, the proposed clock stabling circuit can transform the duty cycle ranging from 10% or 90% to 50% with jitter smaller than 47fs, meeting the requirement of high speed ADCs.