Title :
A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture
Author :
Arima, Yutaka ; Mashiko, Koichiro ; Okada, Keisuke ; Yamada, Tsuyoshi ; Maeda, Atsushi ; Notani, Hiromi ; Kondoh, Harufusa ; Kayano, Shinpei
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0-μm double-poly-Si double-metal CMOS technology. The operation speed is higher than 1×1012 connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses
Keywords :
CMOS integrated circuits; neural nets; branch-neuron-unit architecture; interconnecting multiple chips; operation speed; self-learning neural network chip; CMOS technology; Helium; Integrated circuit interconnections; Large scale integration; Large-scale systems; Network-on-a-chip; Neural networks; Neurofeedback; Neurons; Time sharing computer systems;
Journal_Title :
Solid-State Circuits, IEEE Journal of
