An intelligent subprocessor for hardware emulation with 20-MOPS performance

Author

Nakamura, Hideo ; Sawase, Terumi ; Akao, Yasushi ; Masumura, Shigeki ; Hayashi, Makoto ; Ohsuga, Hiroshi ; Satoh, Yuji ; Aizawa, Tatsuya

Author_Institution

Hitachi VLSI Eng. Corp., Tokyo, Japan

Volume

26

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1662

Lastpage

1668

Abstract

An intelligent subprocessor (ISP) for hardware emulation of embedded controller subsystems is proposed. The subprocessor achieves 20 MOPS and 50-ns resolution of task switching for 12 tasks. It introduces task switching based on a time-slot assignment mechanism, one-clock-per-instruction (CPI) architecture, and parallel processing of a plurality of operations in a single-instruction execution. It also introduces field-programmable internal EPROMs with self-detecting power saving circuits. This subprocessor can emulate simple hardware functions such as timers and serial interfaces, as well as complex hardware functions such as DC motor controllers. A test chip with 90 K transistors was fabricated on a 4.12-mm×4.98-mm area by using 1.3-μm CMOS technology

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; parallel architectures; 13 micron; 20 MHz; 4.98 mm; CMOS technology; VLSI; embedded controller subsystems; field-programmable internal EPROMs; hardware emulation; intelligent subprocessor; one-clock-per-instruction; parallel processing; plurality of operations; self-detecting power saving circuits; single-instruction execution; task switching; test chip; time-slot assignment mechanism; CMOS technology; Central Processing Unit; Circuits; Communication system control; DC motors; Emulation; Hardware; Parallel processing; Real time systems; Registers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.98987

Filename

98987