Title :
CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range
Author :
Gu, Qun Jane ; Jian, Heng-Yu ; Xu, Zhiwei ; Wu, Yi-Cheng ; Chang, Mau-Chung Frank ; Baeyens, Yves ; Chen, Young-Kai
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
fDate :
7/1/2011 12:00:00 AM
Abstract :
To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultra high operation speeds up to 208 GHz, with ultra wide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed X range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.
Keywords :
CMOS integrated circuits; field effect MIMIC; frequency dividers; prescalers; submillimetre wave integrated circuits; CMOS prescaler; dynamic frequency divider topology; frequency 208 GHz; power 2.5 mW; size 65 nm; submillimeter-wave radio-frequency synthesis; time-interleaved dual-injection locking scheme; CMOS integrated circuits; Frequency conversion; Injection-locked oscillators; Resonant frequency; Sensitivity; Transmission line measurements; CMOS prescaler; injection locking frequency divider; submillimeter wave circuits; wide locking range;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2011.2158267
