Title :
Multipurpose high-coding-gain 0.8-μm BiCMOS VLSIs for high-speed multilevel trellis-coded modulation
Author :
Aikawa, Satoru ; Nakamura, Yasuhisa ; Takanashi, Hitoshi
Author_Institution :
NTT Network Syst. Dev. Center, Tokyo, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
Multilevel trellis-coded quadrature-amplitude-modulated (QAM) VLSIs were designed and developed. These VLSIs realize a coding gain of 7.9 dB with SPORT-256 QAM. The VLSIs contain an encoder, mapper, and decoder for trellis-coded 16, 32, 64, 128, and 256 QAM utilizing general mapping. Using small-size and low-power path memory, 150 K gates were achieved using two chips with die sizes of 8 mm×11 mm and 14 mm×14 mm. The VLSIs achieve a maximum data throughput rate of 17 MBd (guaranteed) and 30 MBd (typical) and dissipate only 1 W at a data rate of 17 MBd. The VLSIs also contain a phase ambiguity rejection circuit for a recovered carrier and error pulse generator. The devices are designed with a BiCMOS 0.8-μm process rule. The experimental result of bit-error-rate (BER) performance is presented. The VLSIs are effective for outage-free digital microwave radio systems
Keywords :
BIMOS integrated circuits; VLSI; amplitude modulation; digital integrated circuits; 0.8 micron; 1 W; 7.9 dB; 8 to 14 mm; BER; BiCMOS; QAM; SPORT-256 QAM; bit-error-rate; coding gain; data rate; data throughput; decoder; die sizes; encoder; error pulse generator; experimental result; general mapping; low-power path memory; mapper; multilevel trellis-coded modulation; outage-free digital microwave radio systems; phase ambiguity rejection circuit; quadrature amplitude modulation; recovered carrier; signal-point-reduced trellis-coded QAM; Bandwidth; BiCMOS integrated circuits; Bit error rate; Decoding; Digital signal processing; Gain; Modems; Pulse generation; Quadrature amplitude modulation; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
