• DocumentCode
    1260877
  • Title

    Logic synthesis for ASICs

  • Author

    Damiano, Robert ; Reeves, Douglas S.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    28
  • Issue
    11
  • fYear
    1991
  • Firstpage
    26
  • Lastpage
    33
  • Abstract
    The steps performed by logic synthesis software, which transforms a specification of a function and its timing into an application-specific integrated circuit (ASIC) such as a gate or standard cell array, programmable logic device (PLD), or field programmable gate array (FPGA), are outlined. Hardware description languages, foundry pacts, and testability are discussed. A table describing representative software packages is given.<>
  • Keywords
    application specific integrated circuits; circuit analysis computing; logic CAD; logic arrays; ASICs; cell array; description languages; field programmable gate array; gate; hardware; logic synthesis software; packages; programmable logic device; testability; timing; Application specific integrated circuits; Field programmable gate arrays; Integrated circuit synthesis; Logic circuits; Logic devices; Programmable logic arrays; Programmable logic devices; Software performance; Software standards; Timing;
  • fLanguage
    English
  • Journal_Title
    Spectrum, IEEE
  • Publisher
    ieee
  • ISSN
    0018-9235
  • Type

    jour

  • DOI
    10.1109/6.99013
  • Filename
    99013
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1260877