A 60-GHz 26.3-dB gain 5.3-dB NF low-noise amplifier in 65-nm CMOS using Q-factor enhanced inductors

In this paper, a 60-GHz high gain low-noise amplifier is designed and verified experimentally. Firstly, inductors with asymmetrical ground plane are introduced and studied by using EM simulation, obtains an improvement of quality-factor. Then, a three-stage cascade low-noise amplifier using the proposed inductors is designed. Fabricated in Global Foundries 65-nm CMOS process, the low-noise amplifier features a peak gain of 26.3 dB with 21.8 mW DC power consumption, a noise figure of 5.3 dB, an average output P_1dB of -4 dBm, and a core size of 0.15 mm². In the comparison with prior arts, the proposed design achieves the highest gain and figure-of-merit.