A hybrid CMOS clock divider for PLL of 60GHz transceiver

A hybrid multi-mode clock divider for PLL which used for 60GHz RF transceiver by using both integer-N and fraction-N structure is designed and implemented in this work. Full CMOS digital design is used to implement the circuit to achieve both low power and high flexibility. The digital clock divider includes high speed 3/4 dual modulus prescalar, a 24 modulus divider controller and 3 stage Delta-Sigma Modulator. The divider works up to 3.24GHz. The total power consumption is from 4mW to 9mW based on the different working modes. A MASH111 architecture is selected to implement the fraction-N divider.