DocumentCode
1261246
Title
Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements
Author
Giulietti, A. ; Van der Perre, Liesbet ; Strum, M.
Author_Institution
IMEC, Leuven, Belgium
Volume
38
Issue
5
fYear
2002
fDate
2/28/2002 12:00:00 AM
Firstpage
232
Lastpage
234
Abstract
High-speed, low latency convolutional turbo codes require a parallel decoder architecture. To maximise the gain in speed, the interleaver also should have a parallel structure. Here, a class of optimum parallel interleavers regarding the access to storage elements is presented. They combine regularity (easy implementation) with no latency in data transfer between the decoder module and intrinsic/extrinsic values memories, and show excellent BER performance
Keywords
convolutional codes; interleaved codes; parallel architectures; turbo codes; BER performance; convolutional turbo codes; data transfer; parallel decoder architecture; parallel turbo coding interleavers; regularity; storage elements;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020148
Filename
990214
Link To Document