Title :
A 20-ns 128-kbit×4 high speed DRAM with 330-Mbit/s data rate
Author :
Lu, Nicky C C ; Chao, Hu H. ; Hwang, Wei ; Henkels, Walter H. ; Rajeevakumar, T.V. ; Hanafi, Hussein I. ; Terman, Lewis M. ; Franch, Robert L.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb×4, 78-mm2 chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25°C, and 50-pF load. A 256-b×4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 μm n-well CMOS process
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 1 micron; 128 kbit; 20 ns; 330 Mbit/s; 5 V; 7.5 ns; CMOS IC; column access time; dynamic RAM; high speed DRAM; high-speed page mode; n-well CMOS process; one transistor memory cell; random access time; BiCMOS integrated circuits; CMOS technology; Circuit noise; Delay; Noise generators; Production; Random access memory; Semiconductor device measurement; Signal design; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
