DocumentCode
126176
Title
Capacitive coupling analysis of TSV array in 3D packaging
Author
Luo Guang-Xiao ; Li Er-Ping ; Wei Xing-Chang ; Cui Xiang
Author_Institution
North China Electr. Power Univ., Beijing, China
fYear
2014
fDate
16-23 Aug. 2014
Firstpage
1
Lastpage
4
Abstract
In 3D-TSVs (through silicon vias) interposer layer, the capacitive coupling effects of TSV array are modeled and analyzed for signal transmission. To consider the semiconductor characteristics, the multi-conductor model is presented to model the TSV array by combining the MOS capacitance with the passive RLGC parameters. After that, the values of MOS capacitance and RLGC are extracted. Finally, by using model order reduction, the capacitive coupling characteristic of TSV array is simulated and analyzed for the signal transmission.
Keywords
capacitance; electronics packaging; three-dimensional integrated circuits; 3D packaging; 3D-TSV array; MOS capacitance; capacitive coupling analysis; multiconductor model; passive RLGC parameters; semiconductor characteristics; signal transmission; through silicon vias interposer layer; Analytical models; Arrays; Capacitance; Couplings; Semiconductor device modeling; Silicon; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
General Assembly and Scientific Symposium (URSI GASS), 2014 XXXIth URSI
Conference_Location
Beijing
Type
conf
DOI
10.1109/URSIGASS.2014.6929541
Filename
6929541
Link To Document