DocumentCode
1262766
Title
A 45-Mbit/s CMOS VLSI digital phase aligner
Author
Cordell, Robert R.
Author_Institution
Bell Commun. Res., Red Bank, NJ, USA
Volume
23
Issue
2
fYear
1988
fDate
4/1/1988 12:00:00 AM
Firstpage
323
Lastpage
328
Abstract
An eight-channel, 45-Mb/s digital phase aligner (DPA) has been fabricated in 2-μm CMOS. The device receives asynchronous serial data at a known average clock frequency and unknown phase, and phase-aligns it with a local clock of the same frequency for subsequent synchronous processing. The all-digital architecture of this device minimizes the need for external components and avoids reliance on analog MOS circuitry. Tracking over a phase excursion range of ±4-bit periods has been demonstrated
Keywords
CMOS integrated circuits; VLSI; digital communication systems; digital integrated circuits; 2 micron; 45 MHz; 45 Mbit/s; ASIC; CMOS VLSI digital phase aligner; DPA; all-digital architecture; custom ICs; eight channels; known average clock frequency; local clock; phase excursion; receives asynchronous serial data; subsequent synchronous processing; unknown phase; Circuits; Clocks; Delay effects; Frequency; Signal processing; Switches; Telecommunication network reliability; Temperature; Timing; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.991
Filename
991
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