Bandpass sigma-delta analog-to-digital conversion

Author

Jantzi, S. ; Schreier, Richard ; Snelgrove, M.

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont.

Volume

38

Issue

11

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

1406

Lastpage

1409

Abstract

The traditional low-pass sigma-delta (ΣΔ) analog-to-digital converter is extended to the bandpass case. For input signals with small relative bandwidths, bandpass ΣΔ converters offer high signal-to-noise ratios at significantly lower sampling rates than are required for low-pass ΣΔ converters. A sixth-order single-ended switched-capacitor circuit, clocked at 3 MHz, is designed to convert bandpass signals centered at 455 kHz with 20-kHz bandwidth. Time-domain circuit simulations show that this modulator realizes a 94-dB signal-to-noise ratio for a half-scale input, giving roughly 16-b performance

Keywords

analogue-digital conversion; modulators; switched capacitor networks; 20 kHz; 455 kHz; bandpass case; half-scale input; input signals; relative bandwidths; sampling rates; sigma-delta analog-to-digital conversion; signal-to-noise ratio; signal-to-noise ratios; single-ended switched-capacitor circuit; time-domain circuit simulations; Analog-digital conversion; Bandwidth; Circuit simulation; Clocks; Delta-sigma modulation; Sampling methods; Signal design; Signal to noise ratio; Switched capacitor circuits; Time domain analysis;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.99179

Filename

99179