Title :
A 50-ns CMOS 256 K EEPROM
Author :
Ting, T.-K.J. ; Chang, Thomas ; Lin, Tien ; Jenq, Ching S. ; Naiff, Kenneth L C
Author_Institution :
Microchip Technol. Inc., Chandler, AZ, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
A 32 K×8 EEPROM (electrically erasable programmable read-only memory), which operates with a single 5-V power supply and achieves 100 K cycle endurance, 50-ns typical read access time, and 1-ms page programming time, equivalent to 16 μs/byte, was designed. A double-poly, double-metal, n-well CMOS process with 1.25-μm minimum feature size was developed to manufacture the device. The required and optional extended JEDEC standards for software data protection and chip clear are implemented along with parity check, toggle bit, page-load timer, and data-protection status bit. A modified Hamming code, which uses four parity bits per byte, was implemented to detect and correct single-bit errors
Keywords :
CMOS integrated circuits; EPROM; error correction; error detection; integrated memory circuits; security of data; 1 ms; 1.25 micron; 16 mus; 256 kbit; 5 V; 50 ns; EEPROM; chip clear; cycle endurance; data-protection status bit; double-metal; double-poly; electrically erasable programmable read-only memory; error correction; error detection; extended JEDEC standards; minimum feature size; modified Hamming code; n-well CMOS process; page programming time; page-load timer; parity check; read access time; single 5-V power supply; single-bit errors; software data protection; toggle bit; Clocks; EPROM; Error correction; Iron; Latches; Logic programming; Parity check codes; Programmable logic arrays; Signal generators; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
