An experimental 512-bit nonvolatile memory with ferroelectric storage cell

Author

Evans, J.T. ; Womack, Richard

Author_Institution

Krysalis Corp., Albuquerque, NM, USA

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1171

Lastpage

1175

Abstract

An experimental 512-b random-access memory based on ferroelectric-capacitor storage cells has been successfully fabricated and tested. The device was designed solely for use in process development and electrical characterization and includes onboard test circuitry for that purpose. The internal timing of the memory is controlled externally to allow experimentation with timing algorithms, hence the name 512 externally controlled device, or 512 ECD. The authors discuss the properties of the ferroelectric ceramics used in integrated circuit memories, the operation of a destructively read ferroelectric memory cell, and the organization of the 512 ECD die, including its onboard test circuitry. Finally, retention and wear-out properties of ferroelectric capacitors are discussed as they relate to design requirements

Keywords

CMOS integrated circuits; ferroelectric devices; integrated memory circuits; random-access storage; 3 micron; 30 mW; 5 V; 512 ECD; 512 bit; 512 externally controlled device; 550 ns; NVRAM; RAM; access time; active power; critical feature size; destructively read ferroelectric memory cell; electrical characterization; ferroelectric ceramics; ferroelectric-capacitor storage cells; integrated circuit memories; n-well CMOS process; nonvolatile memory; onboard test circuitry; process development; random-access memory; retention properties; wear-out properties; Capacitors; Ceramics; Circuit testing; Ferroelectric materials; Hysteresis; Nonvolatile memory; Switches; Temperature distribution; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5940

Filename

5940