Title :
Control signal layout ordering scheme minimising cross-coupling effect in deep-submicrometre datapath design
Author :
Yim, Joon-Seo ; Kyung, Chong-Min
Author_Institution :
DSP Group, LG Corp. Inst. of Technol., Seoul, South Korea
fDate :
9/2/1999 12:00:00 AM
Abstract :
In deep submicrometre technology, an inter-wire coupling capacitance dominates wire loading and makes interconnect delays very data-dependent. Reducing this cross-coupling effect is crucial for high-speed lower-power operation. A layout scheme is proposed for datapath control signals which reduces the switching power by 10% and wire delays by 15% for 0.25 μm microprocessor examples
Keywords :
CMOS digital integrated circuits; capacitance; delays; high-speed integrated circuits; integrated circuit interconnections; integrated circuit layout; low-power electronics; microprocessor chips; 0.25 micron; control signal layout ordering scheme; cross-coupling effect minimisation; datapath control signals; deep-submicron datapath design; high-speed lower-power operation; inter-wire coupling capacitance; interconnect layout; microprocessors; switching power reduction; wire delay reduction;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991016
