Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With $\hbox {Si}_{3}\hbox {N}_{4}/\hbox {Al}_{2}\hbox {O}_{3}/\hbox {HfO}_{2}$ Charge-Trapping Layer

A stacked Si₃N₄/HfO₂ charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si₃N₄ to Si and the higher barrier for electron detrapping from HfO₂ to Si₃N₄. The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al₂O₃ between Si₃N₄ and HfO₂ as the CT layer. This is because most of the injecting charges are trapped at the Si₃N₄/Al₂O₃ interface, and Al₂O₃ also provides a high barrier for electron detrapping.