A single D-FET 4-QAM with SC technology

Author

Zhang, Zhangmiao ; Dong, Xuesi ; Zhang, Zhijian

Author_Institution

Dept. of Electron. Eng., Beijing Inst. of Technol., China

Volume

35

Issue

12

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

1551

Lastpage

1552

Abstract

A four-quadrant analog multiplier is described that realizes the multiplication of two signals using the triode-region characteristics of a depletion field-effect transistor (D-FET). The design uses only a single D-FET and associated switched-capacitor circuits. As a result, not only has a simple structure been obtained but also the requirement for matching of the D-FETs (which is inherently imposed on this type of multiplier using multiple D-FETs) is completely removed. By adjusting the width of the clock pulse, it is possible to eliminate the error introduced by mismatching between the capacitances inside the multiplier. A four-quadrant analog multiplier (4-QAM) constructed to verify the operating qualities described is reported to have good characteristics

Keywords

analogue circuits; field effect transistor circuits; switched capacitor networks; SC technology; clock pulse width adjustment; depletion field-effect transistor; four-quadrant analog multiplier; mismatch error elimination; switched-capacitor circuits; triode-region characteristics; Capacitance; Circuits and systems; Clocks; Convolvers; Error analysis; FETs; Quadrature phase shift keying; Signal processing; Space vector pulse width modulation; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.9922

Filename

9922