Improving logic function synthesis, through wire crossing reduction in quantum-dot cellular automata layout

Quantum-dot cellular automata, as the successor of metal-oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.