A 20 K CMOS array with 200-ps gate delay

Author

Boudon, Gerard ; Mollier, Pierre ; Nuez, Jean-paul ; Wallart, Frank ; Bhattacharyya, Arup ; Ogura, Seiki

Author_Institution

IBM France Component Dev. Lab., Corbeil-Essonnes, France

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1176

Lastpage

1181

Abstract

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5-μm channel length FETs is described. The 7.5×7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128×8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware

Keywords

CMOS integrated circuits; VLSI; integrated memory circuits; logic arrays; microprocessor chips; random-access storage; reduced instruction set computing; 0.5 micron; 128 byte; 17 ns; 200 ps; 32 bit; 6.1 ns; 7.5 mm; 8 bit; CMOS gate array prototype; RISC; SRAM; VLSI; access time; automatic placement; cycle time; gate delay; reduced instruction-set computer; CMOS logic circuits; CMOS technology; Computer aided instruction; Delay; FETs; Prototypes; Silicides; Space technology; Titanium; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5941

Filename

5941