Sinusoidal Clock Sampling for Multigigahertz ADCs

Current multigigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock to improve SFDR. Whereas a square-wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but a lower jitter spectrum. To verify this concept, an 8 GS/s, 4b flash ADC with a sinusoidal clock is designed and experimentally measured, achieving a figure-of-merit of 0.86 pJ/conv-step based upon effective resolution bandwidth (ERBW), and 0.2 pJ/conv-step based upon sampling rate.