• DocumentCode
    1265904
  • Title

    A parallel built-in self-diagnostic method for embedded memory arrays

  • Author

    Huang, Der-Cheng ; Jone, Wen-Ben

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Chung-Cheng Univ., Chiayi, Taiwan
  • Volume
    21
  • Issue
    4
  • fYear
    2002
  • fDate
    4/1/2002 12:00:00 AM
  • Firstpage
    449
  • Lastpage
    465
  • Abstract
    In this paper, the authors propose a new built-in self-diagnosis method to simultaneously diagnose spatially distributed memory modules with different sizes. Based on the serial interfacing technique, the serial fault masking effect is observed and a bidirectional serial interfacing technique is proposed to deal with such an issue. By tolerating redundant read/write operations, they develop a new march algorithm called DiagRSMarch to achieve the goals of low test signal routing overhead, tolerable diagnostic time, and high diagnostic coverage. It can be proved that DiagRSMarch can identify all stuck-at, transition, state coupling, and dynamic coupling faults occurring in all memory arrays. Experimental results also demonstrate that the test efficiency of DiagRSMarch is highly dependent on memory topology, defect-type distribution, and degree of parallelism
  • Keywords
    built-in self test; cellular arrays; embedded systems; fault diagnosis; integrated circuit testing; integrated memory circuits; DiagRSMarch; bidirectional serial interfacing technique; defect-type distribution; dynamic coupling faults; embedded memory arrays; high diagnostic coverage; low test signal routing overhead; march algorithm; memory topology; parallel built-in self-diagnostic method; redundant read/write operations; serial fault masking effect; serial interfacing technique; spatially distributed memory modules; state coupling faults; stuck-at faults; tolerable diagnostic time; transition faults; Automatic testing; Built-in self-test; Circuit faults; Computer science; Fault diagnosis; Parallel processing; Random access memory; Routing; Topology; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.992768
  • Filename
    992768