On automatic-verification pattern generation for SoC with port-order fault model

Author

Wang, Chun-Yao ; Tung, Shing-Wu ; Jou, Jing-Yang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

21

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

466

Lastpage

479

Abstract

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage

Keywords

application specific integrated circuits; automatic test pattern generation; combinational circuits; fault simulation; integrated circuit testing; logic testing; sequential circuits; SoC; automatic-verification pattern generation; combinational benchmarks; core-based designs; design verification; port-order fault model; sequential benchmarks; system integrators; system-on-a-chip; undetected port sequence; verification complexity; verification patterns; Availability; Circuit faults; Circuit testing; Design methodology; Integrated circuit interconnections; System testing; System-on-a-chip; Time to market; Uninterruptible power systems; Virtual manufacturing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.992770

Filename

992770