Fault simulation and test algorithm generation for random access memories

Author

Wu, Chi-Feng ; Huang, Chih-Tsun ; Cheng, Kuo-Liang ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

21

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

480

Lastpage

490

Abstract

The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults

Keywords

automatic test pattern generation; fault simulation; integrated circuit testing; random-access storage; RAMSES; TAGS; bit-oriented memory; fault simulation; multiport memory; random access memory; semiconductor memory; software tool; test algorithm generation; word-oriented memory; Algorithm design and analysis; Analytical models; Automatic testing; Circuit faults; Circuit testing; Random access memory; Read-write memory; Semiconductor device testing; Semiconductor memory; Technical Activities Guide -TAG;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.992771

Filename

992771