DocumentCode

1265958

Title

Correction to "Interconnect synthesis without wire tapering"

Author

Alpert, Charles J. ; Devgan, A. ; Fishburn ; Quay, S.T.

Author_Institution

IBM Austin Research Laboratory

Volume

21

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

497

Lastpage

497

Keywords

Design automation; Equations; Laboratories; Microelectronics; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.992775

Filename

992775