DocumentCode
1266081
Title
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies
Author
Ghaida, Rani S. ; Gupta, Puneet
Author_Institution
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Volume
31
Issue
9
fYear
2012
Firstpage
1379
Lastpage
1392
Abstract
Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first-order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and cooptimize design rules, patterning technologies, layout methodologies, and library architectures.
Keywords
circuit optimisation; design for manufacture; electronic engineering computing; integrated circuit layout; integrated circuit manufacture; network topology; DR evaluator; DRE; design for manufacturability; design rule co-evaluation; design rule cooptimization; early evaluation; first-order manufacturability model; first-order variability model; layout congestion-based area estimates; layout manufacturability; layout methodology; layout topology-based area estimates; layout variability; library architectures; patterning technologies; systematic evaluation; technology choices; technology designer; technology development; virtual layouts; virtual standard-cell library; Layout; Logic gates; Metals; Routing; Topology; Transistors; Wires; Design for manufacturability; design rules; layout optimization; patterning; process development; technology assessment;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2012.2192477
Filename
6269964
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