Neural networks in CMOS: a case study

Author

Masaki, Akira ; Hirai, Yuzo ; Yamada, Minoru

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

6

Issue

4

fYear

1990

fDate

7/1/1990 12:00:00 AM

Firstpage

12

Lastpage

17

Abstract

The design of a six-neuron chip using 1.3- mu m CMOS gate-array technology is described. With these neuro-chips, the authors developed a general-purpose neural-network system that can simulate a wide range of neural networks, including Hopfield-type networks, back propagation networks, and many others. The system consists of several neuro-boards and a host computer. Each neuro-board contains 72 neuro-chips, which constitute a network of 54 neurons with 2916 excitatory and 2916 inhibitory synapses. The computer can read and write various registers in the neuro-board, learning algorithms can be executed, and synaptic strength can be easily updated. A hierarchical bus structure of time-sharing buses connects each of the neurons on the wafer. As fabricated, the neuro-WSI uses 0.8- mu m, three-level-metal CMOS gate-array technology.<>

Keywords

CMOS integrated circuits; learning systems; logic arrays; neural nets; 0.8 micron; 1.3 micron; CMOS gate-array technology; Hopfield-type networks; back propagation networks; excitatory synapses; hierarchical bus structure; host computer; inhibitory synapses; learning algorithms; neuro-WSI; neuro-boards; neuro-chips; six-neuron chip; synaptic strength; Biological neural networks; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Computer aided software engineering; Humans; Intelligent networks; Neural networks; Neurons; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.59425

Filename

59425