A model for n-well junction effect on gate-charging damage in PMOSFETs

Author

Lin, Wallace ; Sery, George

Author_Institution

Intel Corp, Santa Clara, CA, USA

Volume

23

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

197

Lastpage

199

Abstract

A quantitative model explaining N-well junction effect on gate charging damage in PMOSFETs is presented. This model takes into account the reverse-biased N-well junction leakage, generated both thermally and by photons and its behavior on limiting charging current passing through gate oxide during plasma processing. The modeling results suggest that plasma illumination plays a key role in enabling gate charging damage in PMOSFETs. The model can also apply to reverse-biased source and drain junctions in both P and NMOSFETs during plasma events.

Keywords

MOSFET; equivalent circuits; leakage currents; plasma materials processing; radiation effects; semiconductor device models; semiconductor device reliability; surface charging; N-well junction effect model; PMOSFETs; equivalent-circuit model; floating-source PMOSFET; gate oxide; gate-charging damage; limiting charging current; photon-induced electron-hole current; plasma illumination; plasma processing; quantitative model; reliability concern; reverse-biased N-well junction leakage; reverse-biased drain junctions; reverse-biased source junctions; thermally generated carriers; CMOS technology; Diodes; Lighting; MOSFET circuits; Photonic integrated circuits; Plasma devices; Plasma materials processing; Plasma sources; Protection; Testing;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.992837

Filename

992837