A/spl uml/nalysis of floating body effects in thin film conventional and single pocket SOI MOSFETs using the GIDL current technique

Author

Din, Najeeb-Ud ; Dunga, Mohan V. ; Kumar, Aatish ; Vasi, J. ; Rao, V. Ramgopal ; Cheng, Baohong ; Woo, J.C.S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. (ITT), Mumbai, India

Volume

23

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

209

Lastpage

211

Abstract

Using a novel gate-induced-drain-leakage (GIDL) current technique and two-dimensional (2-D) simulations, single pocket (SP) SOI MOSFETs have been shown to exhibit reduced floating body effects compared to the homogeneously-doped channel (conventional) SOI MOSFETs. The GIDL current technique has been used to characterize the parasitic bipolar transistor gain for both conventional and SP-SOI MOSFETs. From 2-D device simulations, the lower floating body effects in SP-SOI MOSFETs are analyzed and compared with the conventional MOSFETs.

Keywords

MOSFET; semiconductor device models; semiconductor process modelling; silicon-on-insulator; 2D simulations; Si; gate-induced-drain-leakage; homogeneously-doped channel SOI MOSFET; reduced floating body effects; single pocket technology; thin film devices; Analytical models; Bipolar transistors; Dielectric thin films; Isolation technology; Leakage current; MOSFETs; Semiconductor thin films; Silicon on insulator technology; Tunneling; Two dimensional displays;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.992841

Filename

992841