A double RESURF LDMOS with drain profile engineering for improved ESD robustness

Author

Parthasarathy, V. ; Khemka, V. ; Zhu, R. ; Whitfield, J. ; Bose, A. ; Ida, R.

Author_Institution

SmartMOS Technol., Motorola Inc., Mesa, AZ, USA

Volume

23

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

212

Lastpage

214

Abstract

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I/sub t2/) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size.

Keywords

digital simulation; electrostatic discharge; power MOSFET; protection; safety; semiconductor device breakdown; 100 ns; 100 ns transmission line pulse; 20 V; 5 kV; 50 V; 50 V lateral power MOSFET; ESD protection; LDMOS; breakdown current; deep drain profile; double RESURF; electrostatic discharge; excess of 5 kV; filamentation; holding voltage 20 V; human body model; self-protection; snapback; soft leakage degradation; Breakdown voltage; Current measurement; Degradation; Electrostatic discharge; Immune system; MOSFET circuits; Power MOSFET; Power engineering and energy; Power transmission lines; Pulse measurements;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.992842

Filename

992842